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Lyles College of Engineering

Aaron Stillmaker, Ph.D.

Associate Professor

Electrical & Computer Engineering | 559.278.4823 | Office: EE298

astillmaker@csufresno.edu

Education

University of California, Davis, CA
Ph.D., Electrical and Computer Engineering, 2015
Major: Digital Design and Computer Systems; Minor: Signals and Systems
Dissertation: "Design of Energy-Efficient Many-Core MIMD GALS Processor Arrays in the 1000-Processor Era"
Advisor: Dr. Bevan Baas

University of California, Davis, CA
M.S., Electrical and Computer Engineering, 2013

California State University, Fresno, CA
B.S., Magna Cum Laude, Smittcamp Honors Scholar, 2008
Major: Computer Engineering; Minor:Bussiness

LinkedIn

Courses Taught

Fall 2023:

Fall 2023 Student Success Hours: Via Zoom (you must be logged into your Fresno State Zoom account to join):
https://fresnostate.zoom.us/j/94960668661 
Tuesdays, Wednesdays, and Thursdays from 10 – 11 AM, Mondays from 10:00 AM – 12:30 PM, and by appointment 
Dr. Aaron Stillmaker is the Director of the LCOE Honors Program, and an Associate Professor in the Electrical and Computer Engineering Department in the Lyles College of Engineering at California State University, Fresno. He earned his PhD in 2015 while affiliated with the VLSI Computation Lab in the Electrical and Computer Engineering Department at the University of California, Davis under the advisement of Dr. Bevan Baas. He recieved his BS degree in 2008 in Computer Engineering from the California State University, Fresno in the Smittcamp Family Honors College and his MS degree in 2013 in Electrical and Computer Engineering from the University of California,Davis. Dr. Stillmaker was an Assistant Professor at California State University, Fullerton in Fall 2016. He interned with the Circuit Research Lab under Intel Labs in Hillsboro, OR from September to December 2013. During his undergraduate work he held a long term internship at Pelco Inc.
  • VLSI Design - Verilog
  • VLSI Design - Physical
  • Many-Core Architectures and Design
  • Many-Core Procesing

Google Scholar

  • Peiyao Shi, Aaron Stillmaker, and Bevan M. Baas,
    "Efficient and High-Performance Sparse Matrix-Vector Multiplication on a Many-Core Array,"
    IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Penang, Malaysia, December 2022.
    In press.
  • Renjie Chen, Aaron Stillmaker, and Bevan M. Baas,
    "Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder,"
    IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Patras, Greece, October 2022. 
    In press.
  • Brent Bohnenstiehl, Aaron Stillmaker, Timothy Andreas, and Bevan M. Baas,
    "A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency,"
    IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Patras, Greece, October 2022. 
    In press.
  • Anudeep Bonasu, Aaron Stillmaker, and Shahab Tayeb,
    “Low-Power Vehicular Network ASIC Implementation,” In Proceedings of Latin American Symposium on Circuits and Systems (LASCAS).  February 2022.  Santiago, Chile.
  • Aaron Stillmaker, Brent Bohnenstiehl, Lucas Stillmaker, and Bevan Baas,
    "Scalable Energy-Efficient Parallel Sorting on a Fine-Grained Many-Core Processor Array,"
    Journal of Parallel and Distributed Computing, vol. 138, pp. 32-47, April 2020.
  • Richard Calusdian and Aaron Stillmaker,
    "Hardware Implementation of HEVC Inverse Transform in 45nm CMOS,"
    In Proceedings of the IEEE Latin American Symposium on Circuits and Systems (LASCAS), San Jose, Costa Rica, February 2020.
  • Shylesh Umapathy and Aaron Stillmaker,
    "Impact of Coarse-Grained Power Gate Placement on a Fine-Grained System Design,"
    In Proceedings of the IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodes, Greece, July 2019.
  • Michael Braly, Aaron Stillmaker and Bevan Baas,
    "A Configurable H.265-Compatible Motion Estimation Accelerator Architecture or Realtime 4K Video Encoding in 65nm CMOS,"
    In Proceedings of the IEEE Conference on Dependable and Secure Computing, Taipei, Taiwan, August 2017.
  • Aaron Stillmaker, Brent Bohnenstiehl and Bevan Baas,
    "The Design of the KiloCore Chip,"
    ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2017.  
    Invited.
  • Aaron Stillmaker and Bevan Baas,
    "Scaling Equations for the Accurate Prediction of CMOS Device Performance from 180 nm to 7 nm,"
    Integration, the VLSI Journal, vol. 58, pp. 74-81, June 2017.
  • Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas, "KiloCore: A 32 nm 1000-Processor Computational Array,"
    IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 4, pp. 891-902, April 2017.
    Invited.
  • Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas, "KiloCore: A Fine-Grained 1000 Processor Array for Task Parallel Applications,"
    IEEE Micro, vol.37, no.2, pp. 63-69, March-April 2017.
    Invited.
  • Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas,
    "KiloCore: A 32 nm 1000-Processor Array,"
    In Proceedings of the IEEE HotChips Symposium on High-Performance Chips (HotChips 2016), August 2016.
  • Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas,
    "A 5.8 pJ/Op 115 Billion Ops/sec, to 1.78 Trillion Ops/sec 32nm 1000-Processor Array,"
    IEEE Symposium on VLSI Circuits, Honolulu, HI, June 2016.
  • Aaron Stillmaker
    "Design of Energy-Efficient Many-Core MIMD GALS Processor Arrays in the
    1000-Processor Era    ,"
    Ph.D. Dissertation, Technical Report ECE-VCL-2015-1, VLSI Computation Laboratory,
    ECE Department, University of California, Davis, December 2015.
  • Jon Pimentel, Aaron Stillmaker, Brent Bohnenstiehl and Bevan Baas,
    "Area Efficient Backprojection Computation with Reduced Floating-Point Word Width for SAR Image Formation,"
    IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), Pacific Grove, CA, November 2015.
  • Zheng Cao, Roberto Proietti, Aaron Stillmaker, Nima Mostafavi, Bevan Baas and S. J. Ben Yoo
    "Energy-Efficient, High-Performance, and Reliable Computing with Massively Parallel AsAP and Interconnects,"
    Poster. ACS Productivity Workshop. Catonsville, MD, July 15, 2014.
  • Aaron Stillmaker,
    "Energy-Efficient Sorting on a Many-Core Processor Array,"
    Invited talk. Intel (Intel Labs; Circuit Research Lab). Hillsboro, OR, September 26, 2013.
  • Aaron Stillmaker, Lucas Stillmaker, Brent Bohnenstiehl and Bevan M. Baas,
    "Energy-Efficient Sorting on a Many-Core Platform,"
    Technology and Talent for the 21st Century (TECHCON 2013), Austin, TX, September 2013.
  • Aaron Stillmaker,
    "Energy-Efficient Sorting on a Many-Core Processor Array,"
    Invited talk. Oracle (Sun Microsystems). Santa Clara, CA, March 12, 2013.
  • Aaron Stillmaker, Lucas Stillmaker and Bevan M. Baas,
    "Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array,"
    IEEE International Conference on Parallel and Distributed Systems (ICPADS 2012), Singapore, December 2012.
  • Aaron Stillmaker, and Bevan M. Baas,
    "Modular Sorting on a Fine-Grained Many-Core Processor Array,"
    UC Davis ECE Department Industrial Affiliates Conference 2012, Davis, CA, June 2012.
  • Aaron Stillmaker, Zhibin Xiao and Bevan M. Baas,
    "Toward More Accurate Scaling Estimates of CMOS Circuits from 180 nm to 22 nm,"
    Technical Report ECE-VCL-2011-4, VLSI Computation Laboratory, ECE Department, University of California, Davis, December 2011.
  • Aaron Stillmaker, Zhibin Xiao, Bin Liu, and Bevan M. Baas,
    "Computing Enterprise Workloads With Many-Core Arrays and Special-Purpose Processors,"
    C2S2 Annual Review, Atlanta, GA, October 2011.

Patent

  • Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, and Aaron T. Stillmaker,  “Combined Guaranteed Throughput and Best Effort Network-On-Chip,"
    U.S. Patent Granted May 22, 2018,  Patent Number US 9,979,668 B2 Assigned to Intel Corporation.
    European Patent Filed November 24, 2015, Application number 14873990.4-1857 PCT/US2015062244, Proprietor: Intel Corporation.