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Lyles College of Engineering

KiloCore: A 32-nm 1000-processor Computational Array

Brent Bohnenstiehl *
Aaron Stillmaker *
Jon J. Pimentel *
Timothy Andreas *
Bin Liu *
Anh T. Tran *
Emmanuel Adeagbo *
Bevan M. Baas *

*VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

†Department of Electrical and Computer Engineering
California State University, Fresno


A processor array containing 1000 independent processors and 12 memory modules was fabricated in 32-nm partially depleted silicon on insulator CMOS. The programmable processors occupy 0.055 mm2 each, contain no algorithm-specific hardware, and operate up to an average maximum clock frequency of 1.78 GHz at 1.1 V. At 0.9 V, processors operating at an average of 1.24 GHz dissipate 17 mW while issuing one instruction per cycle. At 0.56 V, processors operating at an average of 115 MHz dissipate 0.61 mW while issuing one instruction per cycle, resulting in an energy consumption of 5.3 pJ/instruction. On-die communication is performed by complementary circuit and packet-based networks that yield a total array bisection bandwidth of 4.2 Tb/s. Independent memory modules handle data and instructions and operate up to an average maximum clock frequency of 1.77 GHz at 1.1 V. All processors, their packet routers, and the memory modules contain unconstrained clock oscillators within independent clock domains that adapt to large supply voltage noise. Compared with a variety of Intel i7s and Nvidia GPUs, the KiloCore at 1.1 V has geometric mean improvements of 4.3× higher throughput per area and 9.4× higher energy efficiency for AES encryption, 4095-b low-density parity-check decoding, 4096-point complex fast Fourier transform, and 100-B record sorting applications.


First Page of the KiloCore MICRO paper
PDF (6.6 MB) [IEEE link],   (c) Copyright 2017, IEEE.


Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas, "KiloCore: A 32-nm 1000-Processor Computational Array," IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 4, pp. 891–902, April 2017.


author = {B. Bohnenstiehl and A. Stillmaker and J. Pimentel and
T. Andreas and B. Liu and A. Tran and E. Adeagbo and
B. Baas},
title = {KiloCore: A 32-nm 1000-Processor Computational Array},
journal = {{IEEE} Journal of Solid-State Circuits ({JSSC})},
year = 2017,
month = apr,
pages = {891--902},
volume = 52,
number = 4